Towards an Asynchronous MIPS Processor

MIPS refers to a series of industry-standard, high-performance, low-power, 32and 64-bit RISC microprocessor architectures and cores for embedded systems produced by MIPS Technologies, Inc. A highly scalable architecture and a flexible licensing strategy render MIPS a very diverse design which wins across a broad spectrum of embedded markets. Examples include Sony PlayStation, Cisco Routers HP Switches etc. As part of a wider research project which aims to develop “An Integrated Framework for Formal Verification and Distributed Simulation of Asynchronous Hardware”, we have embarked on work to develop an asynchronous implementation of the MIPS32 (R3000) architecture. The project is jointly undertaken by the Modelling and Analysis of Systems group at the University of Birmingham, and the AMULET group at the University of Manchester and is funded by EPSRC (Project No. GR/S11091/01 & GR/S11084/01, http://www.cs.bham.ac.uk/~gkt/Research/par-lard/). MIPS32 has 161 instructions in total which can be categorized to groups based on their functionality. Our current asynchronous design supports a subset of those instructions, namely: the memory-reference instructions LW and SW, the arithmetic instructions ADD, SUB, SLT and the branch on equal (BEQ). Two distinct features of MIPS, which render any attempt to design an asynchronous version a very challenging endeavour is the forwarding mechanism and the fact that decisions that the pipeline has to be flushed may be taken at different stages in the pipeline. The paper will discuss possible solutions for both of these problems.